Methods for high integration of semiconductor memory devices (memory) include a method of using sidewall patterning technology to form a data transfer line connected to a memory cell such that the width of the data transfer line is half the minimum dimension of the lithography. However, in such a method, the fluctuation of the width of the mask pattern of the lithography may cause, for example, a wide interconnect width and a narrow interconnect width to occur alternately in adjacent interconnects. Therefore, the interconnect resistance undesirably fluctuates between the interconnects.
Particularly for interconnects having narrow interconnect widths, the read-out speed decreases and the read-out margin decreases as the interconnect delay of the electrical signal increases. As the interconnect resistance increases, electromigration and stress induced migration occur easily; and the reliability of the semiconductor memory device deteriorates.
Although JP-A 2007-194496 (Kokai) discusses a layout regarding contacts between draw out lines and conductive lines having lines and spaces to increase the memory capacity and the reliability, the fluctuation of the interconnect resistance between the interconnects is not mentioned, and there is room for improvement.